Embedded Processing with SoC design and High-Level Synthesis

Reading course at Aarhus University, Department of Engineering

 
 

Study plan

The course will run in Q1, August-October 2014.
The schedule consists of readings and exercises.

It is required that participants have passed the course: "Hardware-software Co-design
of Embedded Systems" (TIHSC1).

Schedule

Week 1:

  • Ch. 1 Introduction
  • Ch. 2 The Zync Device
  • 1. meeting with supervisor
  • Week 2:

  • Ch. 3 Designing with Zynq
  • Ch. 4 Device Comparisons
  • Week 3:

  • Ch. 6 The ZedBoard
  • Ch. 9 Embedded Systems and FPGAs
  • Ex. 1 (Ch. 8) First Designs on Zync
  • 2. meeting with supervisor
  • Week 4:

  • Ch. 10 Zynq System-on-Chip Design Overview
  • Ch. 11 Zynq System-on-Chip Development
  • Ex. 2 (Ch. 12) Next Steps in Zync SoC Design
  • Week 5:

  • Ch. 13 IP Block Design
  • Ch. 14 Spotlight on High-Level Synthesis
  • Ch. 15 Vivado HLS: A Closer Look
  • Week 6:

  • Ch. 17 IP Creation
  • Ch. 19 AXI Interfacing
  • Ex. 3 (Ch. 16) Designing With Vivado HLS
  • 3. meeting with supervisor
  • Week 7:

  • Ch. 20 Adventures with IP Integrator
  • Paper: "High-Level Synthesis for FPGAs:
    From Prototyping to Deployment"
  • Vivado Design Suite User Guide ( UG902):
    Interface Synthesis (pp. 146-171)
    SystemC Synthesis (pp. 386-405)
  • Literature

    The Zynq Book 
    Louise H Crockett and Ross A Elliot, “The Zync Book: Embedded Processing with the ARM Cortex-A9 on the Xilinx Zync-7000 All Programmable SoC”, July 2014.

    Paper 
    Jason Chong et al., “High-Level Synthesis for FPGAs: From Prototyping to Deployment”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions, vol. 30, no. 4, pp. 437-491, 2011.

    Course participants

  • José Maria Górriz
  • Kim Bjerge
  • Links

  • About ASE reading courses
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    Copyright 2014, Aarhus University Department of Engineering.
    Course responsible: Kim Bjerge, kbe@au.dk