High Level Synthesis (HLS)

Reading course at Department of Engineering

 
 

Study plan

The course will run in Q4, April-May 2015.
The schedule consists of readings and exercises. The exercises will be performed with the Xilinx's Vivado tools and the ZedBoard (Zynq).

The students work will cover presentation of papers and a walkthrough of exercises that explores the topics described in the paper.

Schedule

Week 1:

  • Ch. 1 Introduction
  • Ch. 2 The Zync Device
  • Ch. 3 Designing with Zynq
  • Ch. 4 Device Comparisons
  • Why Zynq? (Video tutorial)
  • 1. meeting with supervisor
  • Week 2:

  • Ch. 6.1 to 6.4 The ZedBoard
  • Ch. 9 Embedded Systems and FPGAs
  • Ch. 10 Zynq System-on-Chip Design Overview
  • Ch. 11 Zynq System-on-Chip Development
  • Ex. 1 Embedded System Design Flow on Zynq
  • Week 3:

  • Ch. 13 IP Block Design
  • Ch. 14 Spotlight on High-Level Synthesis
  • Ch. 15 Vivado HLS: A Closer Look
  • 2. meeting with supervisor
  • Ex. 2 High-Level Synthesis Flow on Zynq
  • Week 4:

  • Ch. 18 IP Reuse and intergration
  • Ch. 19 AXI Interface
  • Paper: High-Level Synthesis for FPGAs: From Prototyping to Deployment
  • Ex. 3 Advanced Embedded System Design on Zynq
  • Week 5:

  • SystemC: From The Ground Up ch. 1-10.
    See TIHSC lecture #3 for further lecture description. Exercise is optional.
  • 3. meeting with supervisor
  • Week 6:

  • Paper: TBA (Anders Nedergaard)
  • Paper: TBA (Ryan Damsgaard)
  • Paper: TBA (Kevin Grooters)
  • Student presentations
  • Week 7:

  • Paper: TBA (Anders Ramsing)
  • Paper: TBA (Martin Boel)
  • Paper: TBA (Nicolai Glud)
  • Student presentations
  • Literature

    The Zynq Book 
    Louise H Crockett and Ross A Elliot, The Zync Book: Embedded Processing with the ARM Cortex-A9 on the Xilinx Zync-7000 All Programmable SoC, July 2014.

    SystemC: From The Ground Up
    Black, DC, & Donovan, J 2004, SystemC : From the Ground Up, Kluwer Academic Publishers, Hingham, MA, USA. Available from: ProQuest ebrary. [8 March 2015]. (Require VPN connection)

    Paper 
    Jason Chong et al., High-Level Synthesis for FPGAs: From Prototyping to Deployment, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions, vol. 30, no. 4, pp. 437-491, 2011.

    Course participants

  • Anders Nedergaard
  • Ryan Damsgaard
  • Kevin Grooters
  • Anders Ramsing
  • Martin Boel
  • Nicolai Glud
  • Kim Bjerge
  • Links

  • About reading courses
  • Vivado-Based Workshops
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    Copyright 2015, Aarhus University Department of Engineering.
    Course responsible: Kim Bjerge, kbe@au.dk