Hardware-software Co-design (TIHSC1-U01)
Course Plan 2017 – Q3

 

Last updated: 21. February 2016 by Kim Bjerge kbe@au.dk

 

Semester/quarter: Q3

Place:  Aarhus University, Department of Engineering

   Tuesdays 8:15 – 14:00, 235 Edison

Examination: Oral in 20 minutes, Internal evaluation after the 7-scale

 

Contents:

 

The Course provides a thorough introduction to the methods and techniques for hardware-software co-design and knowledge of how to implement this by using modern digital electronics such as FPGA’s.

The course will teach and train the participants’ ability to implement designs for embedded systems containing both hardware and software components.

 

The course consists of a mixture of lectures and smaller tutorials. A number of mandatory exercises must be approved before you can sign-up for examination.

 

The course will include the following topics:

Learning objectives:

The overall goal for this course is to give the students an introduction to techniques for hardware-software co-design and knowledge of the possibilities offered by modern digital electronics.

Specifically, participants after the course should be able to:

 

 

Lessons Overview:

 

Lesson 1 – Course overview and introduction

Lesson 2 – Methodologies for HW/SW co-design

 

Lesson 3 – SystemC from the ground part 1+2

Lesson 4 – SystemC from the ground part 3

Lesson 5 – Specification and models of computation

 

Lesson 6 – Development with System On Programmable Chips

Lesson 7 – High Level Synthesis

Lesson 8 – Partitioning and Design space exploration

 

Lesson 9 – Use of SysML/UML models in analysis and design

Lesson 10 – HW/SW Co-design projects

 

Lesson 11 – System Synthesis

Lesson 12 – Validation and Verification

 

 

 

TIHSC1-U01 Course Plan 2017, Q3

 

No.

Date

Contents

Literature

 

#1

Tuesday (24/1)

Course overview and introduction

-        Introduction

-        Learning objectives

-        Course plan

-        Exam and exercises

-        Questions before start

 

HW/SW Co-design is the key design technology for digital systems

 

“Hardware/software co-design means meeting system-level objectives by exploiting the synergism of hardware and software through their concurrent design.”

 

HW/SW Co-design Involves:

-        Modeling, process of conceptualizing and refining the specifications by producing a HW/SW model.

-        Validation, process of achieving a reasonable level of confidence that the system will work as designed.

-        Implementation, the physical realization of the hardware (synthesis) and of executable software (compilation).

 

Paper [5]: A Decade of Hardware/Software Codesign, Wayne Wolf

 

Paper [6]:

Specification and Modeling of HW/SW Co-Design for Heterogeneous Embedded Systems

 

 

#2

Tuesday (24/1)

 

Methodologies for HW/SW co-design

 

-        Abstraction Levels

-        System Design Methodology

-        System-Level Models

-        Platform Design

-        System Design Tools

-        Buttom-up

-        Top-down

-        Platform and FPGA

-        System Modeling Language (SpecC, SystemC)

-        Co-design

 

ESD [1]: Chapter 1+(2)

 

 

#3

Tuesday (24/1)

 

 

SystemC from the ground part 1

 

-        Overview – SystemC

-        Abstractions Terminology

-        Transaction-Level Modeling

-        Simulation kernel, Communication and Computation

-        Data types:
Native, Arithmetic, Boolean, Fixed-Point

-        Modules and Threads

-        Notion of Time:
Time, Wait, Start

-        Concurrency:
Events, Notify, Method, Sensitivity

-        Channels:
Basic, Primitive (Fifo, Mutex, Semaphore)

-        Structure:

Top-level, Files

 

System Modelling with SystemC:

-        Start on exercise 1.

 

 

SC [2]: Chapter 1-10

 

Paper [12] optional:

Usage of System Level Modelling with SystemC

 

 

#4

Tuesday (31/1)

 

SystemC from the ground continued part 2+3

 

-        Hierarchical Channels

-        Adaptors for different abstractions of modeling

 

SC [2]: Chapter 1-10

 

 

Tuesday

 (31/1)

 

 

Support on work with exercise 1

 

SC [2]: Chapter 1-10

 

 

 

#5

Tuesday (31/1)

 

Specification and models of computation

 

-        Models of Computation

o   Programming models

o   Process-based models (MPI, KPN, SDF, CSP)

o   State-based models (FSM, FSMD, HCFSMD)

-        System Design Languages (SpecC, SystemC)

-        System Modeling – Abstraction Levels
(Un-timed, Approximate-timed, Cycle-timed)

-        Processor Modeling – HAL, OS

-        System Models – Specification, TLM, CAM

 

ESD [1]: Chapter 3

(Skip 3.5)

 

#6

Tuesday (7/2)

Development with System On Programmable Chips

 

-        Digital Design and VHDL overview

-        Types of IP cores (Soft, Firm, Hard)

-        Categories of IP (DSP, Math, Memory, IO, uP..)

-        System Co-Design with FPGA

-        Processor Architecture

-        Processor Core and Peripheral Selection

-        Hardware and Software Implementation Factors

-        The Zynq All Programmable SoC

 

Introduction to SoC/FPGA design:

-        Start on exercise 2.

 

ZynqBook [4]:

Chapter 1-4

(Skip 2.4, 3.5, 3.6)  

 

 

 

 

Tuesday (7/2)

 

 

Support on work with exercise 2

 

 

 

Tuesday

(14/2)

 

 

Work with exercise 2, no lecture

 

 

#7

Tuesday
(21/2)

 

High Level Synthesis

 

-        From C/C++ to HDL code

-        Control and data path extraction

-        Scheduling and binding

-        Directives and optimization

-        Interface synthesis

-        IP block automation

-        OpenCV synthesis

-        SystemC synthesis

 

ZynqBook [4]:

Ch. 13.1-13.4

IP Block Design

Ch. 14

High-level Synthesis

Ch. 15 (Skim)

 

#8

Tuesday
(21/2)

 

Partitioning and Design Space Exploration (DSE)

 

-        Profiling

-        Mapping (Allocation, Binding and Scheduling)

-        Cost Functions

-        Performance Estimation

-        Worse Case Execution Time (WCET)

-        Metrics, Abstraction, Subsystems

-        Trade-offs

-        Pareto-optimal designs

 

ZynqBook [4]:

Ch. 11 p. 221-225

ESF [3]:

p. 203-207 (Pareto)

p. 208-209  (WCET)

p. 272-277 (Mapping)

 

 

#9

Tuesday (28/2)

Use of SysML/UML models in analysis and design

 

-         Model Based Co-design with SysML/UML
(Analysis, Design and Implementation)

-        Introduction to SysML and MARTE

-        SysML and UML profiles for SystemC

-        SysML for SoC design
Block Definition Diagrams
Internal Block Diagrams
Activity Diagrams

-        System Model Example

 

 

 

 

 

 

 

Project in HW/SW Co-design:

-        Start on exercise 3.

 

Paper [8]: UML2.0 Profiles for Embedded Systems and Systems On a Chip (SoCs)

 

Paper [10]: SysML Profile for SoC Design and SystemC Transformation

 

Paper [9]: Closing the Gap between UML-based Modeling, Simulation and Synthesis of Combined HW/SW Systems

 

Paper [7] optional:

A HW/SW Codesign Methodoloy based on UML

 

 

#10

Tuesday
(28/3)

 

Presentation of HW/SW Co-design projects

 

Support on exercises and group work

 

 

#11

Tuesday (7/3)

System Synthesis

 

-        Traditional board-based design

-        Virtual platform design

-        TLM Based design

-        Application Modeling

-        Platform Definition

-        Computation and communication

-        Load Balancing Algorithm (LBA)

-        Longest Processing Time Algorithm (LPTA)

 

Load balancing algorithm

-        Start on exercise 4.

 

ESD [1]: Chapter 4

 

#12

Tuesday

(7/3)

Validation and Verification

 

-        Validation vs. Verification

-        Simulation based methods

Test-Bench

Coverage

Performance improvements

Stimulus

Monitoring

-        Formal methods
Logic equivalence checking

FSM checking

Model checking

Model Algebra

 

ESD [1]: Chapter 7

 

 

 

Mandatory Exercises:

 

1.     System level modeling using SystemC

2.     Building SoPC designs on a FPGA platform

3.     Project in HW/SW Co-design

4.     Design Space Exploration with the load balancing algorithm

 

 

Literature (Books):

 

[1]  Embedded System Design, Daniel D. Gajski, Samar Abdi, Andreas Gerstlauer, Gunar Schirner (ESD)
Slides and video for all chapters of the book to be found here:
http://www.cecs.uci.edu/embedded-system-design-book/

[2]  SystemC: From The Ground Up, David C. Black, Jack Donovan (SC)

[3]  Embedded System Design, Embedded Systems Foundation of Cyber-Physical Systems, Peter Marwedel, Springer, 2nd Edition (ESF)

[4]  The Zynq Book, Embedded Processing with the ARM Cortex-A9 on the Xilinx Zynq-7000 All Programmable SoC, Louise H. Crockett, Ross A. Elliot, Martin A. Enderwitz, Robert W. Stewart, University of Strathclyde (ZynqBook)
www.zynqbook.com

Additional literature (Will be uploaded on Blackboard):

 

[5]  A Decade of Hardware/Software Codesign, Wayne Wolf
(A_Decade_of_HW_SW_Codesign)

[6]  Specification and Modeling of HW/SW Co-Design for Heterogeneous Embedded Systems
(SpecifcationAndModeling)

[7]  A HW/SW Codesign Methodoloy based on UML
(A_HW_SW_CodesignMethodology)

[8]  UML2.0 Profiles for Embedded Systems and Systems On a Chip (SoCs)
(UML2_0_Profiles_For_ES_and_SoC)

[9]  Closing the Gap between UML-based Modeling, Simulation and Synthesis of Combined HW/SW Systems
(ClosingTheGab)

[10]     SysML Profile for SoC Design and SystemC Transformation
(SysML_Profile_for_SoC)

[11]      Guide for getting started with SystemC development
(SystemC_Getting_Started_artikel)

[12]      Usage of System Level Modelling with SystemC
(UsageOfSystemLevelModelingWithSystemC)